Joren Vaes
The Amp Hour Electronics Podcast
#706 – Leading Edge Analog with Joren Vaes
- Published
- October 18, 2025
- Duration
- 1h 4m
- Summary source
- description
- Last updated
- Apr 29, 2026
Discusses Welcome Joren Vaes, design engineer at SOFICS Simulation is critical when designing analog devices b…
Summary
Welcome Joren Vaes, design engineer at SOFICS Simulation is critical when designing analog devices based on a PDK from the fab Parasitics are significant, especially with new nodes having upwards of 16 metal layers Chris complained about a class where the professor made them draw planar structures with graph paper with colored pencils Large fabs on leadin…
Show notes
Welcome Joren Vaes, design engineer at SOFICS Simulation is critical when designing analog devices based on a PDK from the fab Parasitics are significant, especially with new nodes having upwards of 16 metal layers Chris complained about a class where the professor made them draw planar structures with graph paper with colored pencils Large fabs on leading edge nodes have 1800 page textbook of rules Because the constraints get tighter, that book gets longer for each node 2 nm mass production on